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High Frequency Limitations of Diode Frequency Multipliers

Authors:
Jack East
Abstract:
A computer program has been written to investigate the design tradeoffs of high frequency diode frequency multipliers. Velocity saturation and breakdown have been included in a device model that is part of a nonlinear multiple reflection simulation. The device doping, epitaxial layer length and velocity vs. electric field curve are input parameters. The program has a search routine to match the diode input impedance and to optimize the load impedance to maximize the efficiency. The DC bias point choice varies the operation from a resistive to a reactive mode. A useful measure of the operating point is the input Q. Lower Q's correspond to more resistive operation and higher Q's correspond to varactor operation. The input Q also determines the ease of matching and the resulting sensitivity of the circuit design to small changes. This computer program has been used to investigate diode multiplier operation over an input frequency range from 100 to 300 GHz. The results give useful insight into diode multipliers. The optimum multiplier design for power is shown to be different than the optimum efficiency design. The best results at lower frequencies are varactor designs. The designs become more resistive with increasing frequency. The paper will give design details and a physical description of the tradeoffs.
Categories:
Multipliers, Sources
Year:
1996
Session:
2
Full-text:
Download a PDF of this paper.
Page Number(s):
116-124