ISSTT Proceedings

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E-Beam SIS Junction Fabrication Using CMP and E-Beam Defined Wiring Layer

Authors:
Patrick Puetz, Karl Jacobs
Abstract:
High frequency (> 0.5 THz) circuit design of SIS mixer elements used in radioastronomical heterodyne receivers demand tightly controlled junction areas with sizes smaller than 0.5 µm², suggesting the use of electron beam lithography (EBL). The thin PMMA electron beam resist, however, cannot be used for the usual self-aligned liftoff of the insulating dielectric. We implemented a new processing scheme similar to the PARTS (Planarized All-Refractory Technology for Superconducting electronics) fabrication process developed at IBM. In this process a chemical mechanical polishing (CMP) step is used to planarize the dielectric (Si02). CMP of the circuits on fused quartz substrates was performed on a standard lapping machine with a simple motorized polishing head. Dielectric thickness variations across the active chip diameter (0 20 mm) of only ± 20 nm were achieved. In order to test the quality of our junction fabrication, square and rectangular junctions with areas ranging from 0.02 µm² to 25 µm² were fabricated and DC-tested. We further investigated EBL for the wiring layer, thus extending the process to a precise definition and positioning accuracy of all critical circuit geometries. This is especially interesting for tuning circuits at 1 THz and beyond, with typical lengths and widths in the order of a few microns. First results indicate that junctions with EBL defined wiring layers can have the same quality as those with UV defined wiring.
Categories:
Mixers, Schottky Devices
Year:
1999
Session:
2
Full-text:
Download a PDF of this paper.
Page Number(s):
118-129