ISSTT Proceedings

ISSTT Proceedings

You searched for:search icon

No Keywords
Showing 0 of items from your search. Start over 

Monolithic Millimeter-wave and Submillimeter-wave Integrated Circuit (MMIC and S-MMIC) Testing Capabilities at JPL up to 500 GHz

Authors:
Lorene Samoska, A. K. Fung, Todd C. Gaier, W. R. Deal, V. Radisic, X.B. Mei, R. Lai
Abstract:
Over the years, our group has been developing on-wafer and waveguide testing capabilities for MMIC amplifiers, oscillators, transistors, and diode circuits up to 500 GHz. In this work, we outline the present state-of-the-art in terms of on-wafer S-parameter measurements, onwafer noise figure measurements, and on-wafer power measurements up to 350 GHz for a variety of MMIC and new Submillimeter-wave MMIC (S-MMICs) chips. The first S-MMIC chips are described in Reference 1 and were tested at JPL and fabricated at NGST, and include single stage HEMT amplifiers with 2.5 dB of gain at 300 GHz. Figure 1a, below, shows the on-wafer full 2-port vector network analyzer test set used for the measurements up to 325 GHz. Several years ago we reported the state-of-the-art in HEMT doubler technology up to 320 GHz using on-wafer test equipment outside of its recommended frequency range, which resulted in large uncertainty in measured power data. Today, together with GGB Industries and OML Laboratories, we have developed the submillimeter-wave test sets to measure noise figure and power data to within 1 dB of accuracy on-wafer. Below in Figure 1b is a photograph of our on-wafer noise figure test set, capable of less than +/- 1 dB accuracy up to 270 GHz.
Categories:
Devices, Measurements & Calibration
Year:
2007
Session:
11
Full-text:
Download a PDF of this paper.
Page Number(s):
284